1. Technical Field of the Invention
The present invention relates generally to analog switches, and more particularly to MOS analog switches.
2. Description of Related Art
Reference is now made to FIG. 1 which shows a schematic diagram of a prior art MOS analog switch 10. The switch 10 is formed from an NMOS transistor 12 and a PMOS transistor 14 that are connected in parallel. More specifically, the source of the NMOS transistor 12 is connected to the drain of the PMOS transistor 14 (at node 16), and the drain of the NMOS transistor 12 is connected to the source of the PMOS transistor 14 (at node 18). The input signal at the terminal IN is applied to node 16 and the output signal at the terminal OUT is taken from node 18. A control signal at the terminal CONTROL is applied to gate of NMOS transistor 12, while the complement of the control signal is applied to the gate of the PMOS transistor 14 through the operation of an inverter 20. When the control signal is logic low, the NMOS transistor 12 and PMOS transistor 14 are both turned off so as to isolate the input terminal IN from the output terminal OUT. When the control signal is logic high, however, the NMOS transistor 12 and PMOS transistor 14 are both turned on, and a signal at the input terminal IN is coupled by the analog switch 10 to the output terminal OUT.
The analog switch 10 is used in many applications. For example, the switch 10 is used in audio applications to control passage of an analog audio signal from IN to OUT. When used in audio applications, however, it is important that the analog switch 10 exhibit a low flatness characteristic. “Flatness” refers to the difference between the maximum value of on-resistance for the switch 10 and the minimum value of on-resistance for the switch 10 over a range of voltage input levels. The lower the flatness (i.e., the more flat the on-resistance of the switch 10 as a function of input voltage), the better; especially in audio applications where flatness can be correlated to sound quality (and non-flatness correlated to signal distortion). The circuit of FIG. 1 does not exhibit a flatness which is acceptable for many audio (and other) applications.
Reference is now made to FIG. 2 which shows a schematic diagram of a prior art MOS analog switch 50 (as taught by U.S. Pat. No. 6,154,085, the disclosure of which is hereby incorporated by reference). The switch 50 has an improved low flatness operating characteristic in comparison to switch 10 of FIG. 1. This is accomplished by regulating the gate voltage according to the signal source. First NMOS transistor 52 has its source coupled to the input terminal IN, and its drain coupled to the output terminal OUT. Second NMOS transistor 54 has its source coupled to the input terminal IN and its drain coupled to node 56. Third NMOS transistor 58 has its source coupled to the node 56 and its drain coupled to the output terminal OUT. A control signal at the terminal CONTROL is applied to the gates of transistors 52, 54 and 58. Node 56 is further coupled to the bulk terminals (substrate wells) of transistors 52, 54 and 58. The switch 50 further includes a level shifter 60 whose input is coupled to the node 56 and whose output is coupled to the gates of transistors 52, 54 and 58 through an optional resistor 62.
When the switch 50 is turned on by the control signal, the circuit functions to provide a constant gate drive to NMOS transistor 52, regardless of the input signal received at terminal IN, in order to maintain a substantially constant on-resistance for the switch 50 (i.e., achieve low flatness). The level shifter 60 accomplishes this by providing a constant gate-to-source voltage relative to the midpoint of the source-to-drain voltage of transistor 52. The transistors 54 and 58 provide a voltage at node 56 which is at the midpoint between the source voltage and drain voltage of transistor 52. The level shifter 60 shifts the signal voltage at the input terminal IN by an amount equal to the desired gate-to-source voltage of the transistor 52, and provides the fixed gate-to-source voltage with respect to the source-to-drain voltage.
There are limitations with respect to the switch 50 of FIG. 2. The level shifter 60 requires a constant current to operate (see, '085 patent, FIG. 3), and this not preferred in battery powered (for example, mobile) applications. Additionally, if the input signal at terminal IN goes to far negative (for example, −1 Volt), the output of the level shifter 60 will be clamped to zero volts.
There is accordingly a need in the art for an improved analog switch exhibiting a low flatness operating characteristic and suitable for use in battery powered applications.